The invention relates to an integrated memory whose memory cells are connected to plate lines.
U.S. Pat. No. 5,592,410 describes a ferroelectric memory in the form of an FRAM or FeRAM (Ferroelectric Random Access Memory). Its memory cells have selection transistors and storage capacitors. The storage capacitors have a ferroelectric dielectric which can assume different polarization states depending on a stored logic state. The polarization state influences the capacitance of the storage capacitor. One electrode of each storage capacitor is connected to a bit line of the memory via the corresponding selection transistor. A control terminal of the selection transistor is connected to a word line of the memory. A second electrode of the storage capacitor is connected to a plate line. During a read access, the selection transistor is turned on and the potential of the plate line is pulsed from a low potential to a high potential. The change in the potential on the bit line connected to the memory cell is subsequently evaluated. It is a measure of the polarization-dependent capacitance of the storage capacitor and therefore serves for ascertaining the respective logic state that is stored.
In U.S. Pat. No. 5,592,410, the word lines run perpendicularly to the bit lines and the plate lines run parallel to the word lines. Each plate line is connected to the same output of a word decoder, to which the associated word line is also connected. Thus, through activation of one of the word lines, the associated plate line is always simultaneously activated as well. The result of this is that all of the memory cells which are selected via the respectively activated word line influence the potential on the associated bit line through the pulsed signal on the plate line connected to them.
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide an integrated memory having memory cells with storage capacitors that are connected to plate lines, and in which, upon activation of a word line, only the potential on a portion of the bit lines which are crossed by the word line is influenced by pulsed signals on the plate lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, that includes: bit lines; word lines; crossover points where the bit lines crossover the word lines; and memory cells that are configured at the crossover points. Each one of the memory cells includes at least one selection transistor having a control terminal that is connected to one of the word lines. Each one of the memory cells includes a storage capacitor having a first electrode that is remote from the selection transistor and having a second electrode. The selection transistor connects the second electrode of the storage capacitor to one of the bit lines. The memory also includes plate lines for carrying pulsed signals. Each one of the plate lines is connected to the first electrode of the storage capacitor of a respective one of the memory cells. The plate lines are configured parallel to the bit lines. The memory also includes a row decoder for addressing the word lines, and a column decoder for selecting at least one of the plate lines in dependence on a column address. The memory also includes sense amplifiers for amplifying data that are read from the memory cells. Each one of the sense amplifiers are respectively connected to at least two of the bit lines, which are assigned different column addresses. The memory also includes control units for performing a function that is selected from the group consisting of supplying input signals to the sense amplifiers, forwarding output signals from the sense amplifiers, and activating the sense amplifiers, the control units including first switching elements and second switching elements. The memory also includes data lines for transferring the data that have been read from the memory cells and that have been amplified by the sense amplifiers. The second switching elements connect the data lines to the sense amplifiers. A respective one of the plate lines and at least one of the bit lines are connected to the same one of the memory cells. The sense amplifiers are connected to a respective one of the bit lines by a respective one of the first switching elements. Each one of the first switching elements includes a control terminal that is connected to the column decoder. Each one of the second switching elements includes a control terminal. The plate lines define groups of the plate lines. Each one of the groups of the plate lines is respectively assigned to the at least two of the bit lines that are connected to a respective one of the sense amplifiers. Each one of the groups of the plate lines is connected, using an OR function, to the control terminal of one of the second switching elements which is connected to a respective one of the sense amplifiers.
In accordance with an added feature of the invention, the plate lines which are connected to the storage capacitors of the memory cells are arranged parallel to the bit lines. A respective one of the plate lines and at least one of the bit lines are connected to the same memory cell. A column decoder serves for selecting one of the plate lines in a manner that is dependent on a column address that is present.
Thus, whereas in U.S. Pat. No. 5,592,410 the plate lines run parallel to the word lines and are connected to outputs of the word line decoder, in the invention disclosed herein, the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.
In accordance with an additional feature of the invention, the integrated memory has control units for influencing a data transfer from the bit lines to a point outside the memory, which each have a control input which is connected to a respective output of the column decoder via one of the plate lines.
In this development, then, the plate lines serve for communicating control signals from the column decoder to the control units.
In accordance with another feature of the invention, the control units are, for example, first switching elements via which the bit lines are connected to sense amplifiers.
In accordance with a further feature of the invention, the control units are activation units which are each assigned to one of the sense amplifiers and serve for activating the respective sense amplifier.
In accordance with a further added feature of the invention, the control units are second switching elements, via which, the sense amplifiers are connected to data lines which serve for transferring data that have been read from the memory cells and have been amplified by the sense amplifiers.
In accordance with a concomitant feature of the invention, the storage capacitor of each one of the memory cells includes a ferroelectric dielectric.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in integrated ferroelectric memory whose plate lines are selected by the column decoder, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.